1. Field of the Invention
The present invention is directed to testing integrated circuits. More specifically, but without limitation thereto, the present invention is directed to parametric testing of an integrated circuit.
2. Description of Related Art
Parametric testing is used to verify that the input thresholds for logic zero and logic one of an integrated circuit meet performance specifications. Typically, the chip inputs are connected to a test pattern generator, and the output of each chip input buffer is connected to one input of a NAND gate to form a chain or logic tree of NAND gates. If all chip input buffers are performing properly, then the output of the last NAND gate in the logic tree will transition each time a single input of the chip changes from a one to a zero or from a zero to a one provided that all the chip inputs below the changed input are equal to a one. A fault is detected if the output of the logic tree does not toggle when one of the chip inputs toggles.